As reductions in device scaling continue front-end-of-line (FEOL) transistor size becomes smaller and the number of transistors per unit area increases. Correspondingly, back-end-of-line (BEOL) metal interconnect line pitch decreases. In advanced chip manufacturing, the standard method of fabricating a BEOL metal interconnect layer employs a copper (Cu) damascene process. As illustrated in FIG. 1A, a dielectric layer 101 is formed over transistor 103 and substrate 105, and a dual layer hard mask 107 is formed on dielectric layer 101. Trenches 109 and vias/contact openings 111 (down to metal contact 113) are formed by lithographically patterning hard mask 107 and etching dielectric 101 through the patterned hard mask. Hard mask 107 protects the dielectric surface from etch damage. However, due to the material and etch rate differences between hard mask 107 and dielectric 101, etch undercut occurs at the dielectric interface area below the hard mask (shown at 115).
Adverting to FIG. 1B, the process continues with deposition of a barrier layer and seed layer 117 (known as a metal liner) in trenches 109 and vias/contact openings 111. Barrier/seed layer 117, however, cannot be deposited with good integrity across the undercut areas. The interface between the barrier metal and the dielectric in the vicinity of the etch undercut is degraded, thereby causing side wall voiding, or slits, and dendrite problems later in the process. In addition, as the metal trench width is reduced and the trench aspect ratio increases (for example, from 2.2 for a metal wiring pitch of 136 nm to 2.6 for a wiring pitch of 90 nm, to as high as 2.9 for a wiring pitch of 50 nm), it is becoming increasingly challenging to deposit barrier/seed layers into such high aspect ratio features with good uniformity and integrity. Furthermore, since the trench critical dimension (CD) to barrier/seed layer thickness ratio is already close to 4:1 for 22 nm node technologies, deposition of barrier/seed layer will be particularly difficult for 20 nm technology node technologies and beyond with current plasma vapor deposition (PVD) techniques.
FIG. 1C illustrates the next step, plating of Cu 119. The high aspect ratio trenches with etch undercut are also difficult to fill with metal during plating, because metals grow from the side walls and “pinch off” the trench inlet before the trench is completely filled with metal. As the inlet becomes closed, thereby preventing further flow into the trench, voids result in the metal, causing “hollow metal” defects. In addition, poor inner edge coverage becomes the source of nodules, or dendrites, in a later CMP step.
Subsequently, as illustrated in FIG. 1D, CMP is performed to remove excess metal and hard mask 107, and to planarize the surface. However, the final surface includes dishing, as shown at 121, and residue metal, or dendrites, 123, resulting from the aforementioned voids and also from the process of removing the hard mask near the undercut region.
A need therefore exists for methodology enabling the formation of metal interconnects with reduced metal void and dendrite defects.